23 search results - page 2 / 5 » Acceleration of Linear Block Code Evaluations Using New Reco... |
FPGA
2010
ACM
13 years 5 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
ICS
2009
Tsinghua U.
14 years 9 days ago
2009
Tsinghua U.
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
INFOCOM
2009
IEEE
14 years 5 days ago
2009
IEEE
—The performance of randomized network coding can suffer significantly when malicious nodes corrupt the content of the exchanged blocks. Previous work have introduced error corr...
TASLP
2011
13 years 14 days ago
2011
Abstract—The shifted delta cepstrum (SDC) is a widely used feature extraction for language recognition (LRE). With a high context width due to incorporation of multiple frames, S...