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» Achieving Agility through Architecture Visibility
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 10 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
RV
2009
Springer
155views Hardware» more  RV 2009»
13 years 10 months ago
Hardware Supported Flexible Monitoring: Early Results
Monitoring of software’s execution is crucial in numerous software development tasks. Current monitoring efforts generally require extensive instrumentation of the software or d...
Antonia Zhai, Guojin He, Mats Per Erik Heimdahl