6 search results - page 1 / 2 » Activity-Aware Registers Placement for Low Power Gated Clock... |
ISVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ICCD
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...