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» Adaptive Channel Buffers in On-Chip Interconnection Networks...
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ICC
2007
IEEE
140views Communications» more  ICC 2007»
13 years 11 months ago
Performance Analysis of Adaptively-Routed Wormhole-Switched Networks with Finite Buffers
—The use of adaptively-routed wormhole switched k-ary n-cubes has been motivated by the high path diversity provided by the rich topology of this family of interconnection networ...
Nasser Alzeidi, Mohamed Ould-Khaoua, Lewis M. Mack...
ANCS
2007
ACM
13 years 9 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 5 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
IWCMC
2006
ACM
13 years 11 months ago
Cross-layer performance analysis of joint rate and power adaptation schemes with multiple-user contention in Nakagami fading cha
Adaptively adjusting transmission rate and power to concurrently enhance goodput and save energy is an important issue in the wireless local area network (WLAN). However, goodput ...
Li-Chun Wang, Kuang-Nan Yen, Jane-Hwa Huang, Ander...
IWCMC
2009
ACM
13 years 11 months ago
Performance analysis and adaptive power control for block coded collaborative networks
We derive theoretical bit and frame error rate expressions for decode-and-forward (DF) collaborative networks containing M users, employing a variety of block codes over a Rayleig...
W. Guo, Ioannis Chatzigeorgiou, Ian J. Wassell, Ro...