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» Adaptive Concretization for Parallel Program Synthesis
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IPPS
2009
IEEE
13 years 12 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...
ICDCS
1997
IEEE
13 years 9 months ago
Concurrency Control and View Notification Algorithms for Collaborative Replicated Objects
—This paper describes algorithms for implementing a high-level programming model for synchronous distributed groupware applications. In this model, several application data objec...
Robert E. Strom, Guruduth Banavar, Kevan Miller, A...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
13 years 12 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...