44 search results - page 2 / 9 » Adaptive SRAM memory for low power and high yield |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
—Reducing energy consumption is an important issue for battery powered embedded computing systems. Content Addressable Memory (CAM)-based Highly-Associative Caches (HAC) are wide...
PATMOS
2010
Springer
13 years 3 months ago
2010
Springer
Abstract. Portable digital systems tend to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to pr...
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...