18 search results - page 1 / 4 » Adaptive line placement with the set balancing cache |
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
IMS
2000
13 years 8 months ago
2000
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
SIAMCOMP
2008
13 years 4 months ago
2008
We develop approximation algorithms for the problem of placing replicated data in arbitrary networks, where the nodes may both issue requests for data objects and have capacity fo...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...