18 search results - page 3 / 4 » Adaptive line placement with the set balancing cache |
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
MICRO
2009
IEEE
14 years 4 days ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
SC
2003
ACM
13 years 10 months ago
2003
ACM
We develop and evaluate a system for load management in shared-disk file systems built on clusters of heterogeneous computers. The system generalizes load balancing and server pr...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Data Grids provide geographically distributed resources for large-scale data-intensive applications that generate large data sets. However, ensuring efficient access to such huge...