13 search results - page 1 / 3 » Adaptive set pinning: managing shared caches in chip multipr... |
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
HIPEAC
2009
Springer
13 years 8 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
HPCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
IEEEPACT
2008
IEEE
13 years 11 months ago
2008
IEEE
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...