13 search results - page 3 / 3 » Adaptive set pinning: managing shared caches in chip multipr... |
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
SC
1995
ACM
13 years 8 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
ISCA
2010
IEEE
13 years 6 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...