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ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
11 years 8 months ago
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradig...
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
TODAES
2008
115views more  TODAES 2008»
10 years 11 months ago
Automata-based assertion-checker synthesis of PSL properties
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
Marc Boule, Zeljko Zilic
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
11 years 4 months ago
Enabling efficient post-silicon debug by clustering of hardware-assertions
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
Mohammad Hossein Neishaburi, Zeljko Zilic
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