11 search results - page 1 / 3 » Address-Independent Estimation of the Worst-case Memory Perf... |
TII
2010
12 years 11 months ago
2010
Abstract--Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution finishes within lower and upper specified bounds...
RTSS
1994
IEEE
13 years 8 months ago
1994
IEEE
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
RTAS
1996
IEEE
13 years 8 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
ANCS
2009
ACM
13 years 2 months ago
2009
ACM
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...