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» Addressing Queuing Bottlenecks at High Speeds
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2004
Tsinghua U.
13 years 10 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
INFOCOM
2002
IEEE
13 years 9 months ago
Scalable IP Lookup for Programmable Routers
Abstract— Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services...
David E. Taylor, John W. Lockwood, Todd S. Sproull...
MM
2010
ACM
121views Multimedia» more  MM 2010»
13 years 5 months ago
Implementation and demonstration of a credit-based home access point
The increasing availability of high speed Internet access and the decreasing cost of wireless technologies has increased the number of devices in the home that wirelessly connect ...
Choong-Soo Lee, Mark Claypool, Robert E. Kinicki
ICCD
2008
IEEE
221views Hardware» more  ICCD 2008»
14 years 1 months ago
Reversi: Post-silicon validation system for modern microprocessors
— Verification remains an integral and crucial phase of today’s microprocessor design and manufacturing process. Unfortunately, with soaring design complexities and decreasing...
Ilya Wagner, Valeria Bertacco