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LCTRTS
2007
Springer
13 years 9 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
IPPS
1996
IEEE
13 years 7 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
13 years 9 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
APCSAC
2003
IEEE
13 years 9 months ago
Reducing Access Count to Register-Files through Operand Reuse
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
HPCA
2011
IEEE
12 years 7 months ago
Exploiting criticality to reduce bottlenecks in distributed uniprocessors
Composable multicore systems merge multiple independent cores for running sequential single-threaded workloads. The performance scalability of these systems, however, is limited d...
Behnam Robatmili, Madhu Saravana Sibi Govindan, Do...