9 search results - page 1 / 2 » Advanced SAT-Techniques for Bounded Model Checking of Blackb... |
MTV
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we will present an optimized structural 01X-SAT-solver for bounded model checking of blackbox designs that exploits semantical knowledge regarding the node selection...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...