Sciweavers

Share
67 search results - page 1 / 14
» Aggregating processor free time for energy reduction
Sort
View
CODES
2005
IEEE
10 years 5 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CODES
2008
IEEE
10 years 6 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
CF
2005
ACM
10 years 1 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
ISCA
2003
IEEE
107views Hardware» more  ISCA 2003»
10 years 5 months ago
Positional Adaptation of Processors: Application to Energy Reduction
Although adaptive processors can exploit application variability to improve performance or save energy, effectively managing their adaptivity is challenging. To address this probl...
Michael C. Huang, Jose Renau, Josep Torrellas
ESTIMEDIA
2009
Springer
9 years 9 months ago
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories
Abstract--Memory accesses are a major cause of energy consumption for embedded systems and the stack is a frequent target for data accesses. This paper presents a fully software te...
Lovic Gauthier, Tohru Ishihara
books