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TVLSI
2002
102views more  TVLSI 2002»
13 years 4 months ago
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
Ramesh Karri, Kaijie Wu
ITC
2000
IEEE
110views Hardware» more  ITC 2000»
13 years 9 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu
DATE
2002
IEEE
122views Hardware» more  DATE 2002»
13 years 9 months ago
Exploiting Idle Cycles for Algorithm Level Re-Computing
Although algorithm level re-computing techniques can trade-off the detection capability of Concurrent Error Detection (CED) vs. time overhead, it results in 100% time overhead whe...
Kaijie Wu, Ramesh Karri
DAC
2001
ACM
14 years 5 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
MSO
2003
13 years 6 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris