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LCTRTS
2007
Springer
13 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
13 years 11 months ago
Mapping multi-dimensional signals into hierarchical memory organizations
The storage requirements of the array-dominated and looporganized algorithmic specifications running on embedded systems can be significant. Employing a data memory space much l...
Hongwei Zhu, Ilie I. Luican, Florin Balasa
CODES
2003
IEEE
13 years 10 months ago
A multiobjective optimization model for exploring multiprocessor mappings of process networks
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
EMSOFT
2007
Springer
13 years 9 months ago
A unified practical approach to stochastic DVS scheduling
This paper deals with energy-aware real-time system scheduling using dynamic voltage scaling (DVS) for energy-constrained embedded systems that execute variable and unpredictable ...
Ruibin Xu, Rami G. Melhem, Daniel Mossé
LCTRTS
2010
Springer
13 years 3 months ago
Improving both the performance benefits and speed of optimization phase sequence searches
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...