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» Algorithms for a switch module routing problem
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DATE
2006
IEEE
87views Hardware» more  DATE 2006»
14 years 1 days ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
EURONGI
2008
Springer
13 years 7 months ago
Interference-Aware Channel Assignment in Wireless Mesh Networks
DED ABSTRACT The increased popularity and the growth in the number of deployed IEEE 802.11 Access Points (APs) have raised the opportunity to merge together various disjointed wire...
Rosario Giuseppe Garroppo, Stefano Giordano, David...
ICPP
2007
IEEE
14 years 9 days ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
SIGCOMM
2010
ACM
13 years 6 months ago
Generic and automatic address configuration for data center networks
Data center networks encode locality and topology information into their server and switch addresses for performance and routing purposes. For this reason, the traditional address...
Kai Chen, Chuanxiong Guo, Haitao Wu, Jing Yuan, Zh...
ICCAD
2006
IEEE
139views Hardware» more  ICCAD 2006»
14 years 2 months ago
Analog placement with symmetry and other placement constraints
In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for ...
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N...