44 search results - page 2 / 9 » Allocator implementations for network-on-chip routers |
TON
2008
13 years 4 months ago
2008
Given a set of demands between pairs of nodes, we examine the traffic engineering problem of flow routing and fair bandwidth allocation where flows can be split to multiple paths ...
INFOCOM
2002
IEEE
13 years 10 months ago
2002
IEEE
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
JHSN
2000
13 years 5 months ago
2000
Fair allocation of available bandwidth to competing flows is a simple form of quality of service (QoS) that can be provided to customers in packet-switched networks. A number of p...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
RTSS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...