13 search results - page 1 / 3 » An 8x8 run-time reconfigurable FPGA embedded in a SoC |
DAC
2008
ACM
14 years 5 months ago
2008
ACM
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
IWSOC
2003
IEEE
13 years 9 months ago
2003
IEEE
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
DAC
2004
ACM
13 years 8 months ago
2004
ACM
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
DFT
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ERSA
2003
13 years 5 months ago
2003
Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an applicati...