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ISPASS
2007
IEEE
13 years 11 months ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...
EUROPAR
1999
Springer
13 years 9 months ago
A Study of a Simultaneous Multithreaded Processor Implementation
This paper describes an approach to the implementation and the operation of a Simultaneous Multithreaded processor. We propose an architecture which integrates a software mechanism...
Dominik Madon, Eduardo Sanchez, Stefan Monnier
HPCA
2006
IEEE
14 years 5 months ago
The common case transactional behavior of multithreaded programs
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen...
ISPASS
2006
IEEE
13 years 11 months ago
Considering all starting points for simultaneous multithreading simulation
Commercial processors have support for Simultaneous Multithreading (SMT), yet little work has been done to provide representative simulation results for SMT. Given a workload, cur...
Michael Van Biesbrouck, Lieven Eeckhout, Brad Cald...
SPAA
1990
ACM
13 years 9 months ago
Analysis of Multithreaded Architectures for Parallel Computing
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...
Rafael H. Saavedra-Barrera, David E. Culler, Thors...