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MICRO
1996
IEEE
97views Hardware» more  MICRO 1996»
13 years 9 months ago
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...
Daniel M. Lavery, Wen-mei W. Hwu
ASAP
2009
IEEE
131views Hardware» more  ASAP 2009»
13 years 10 months ago
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system
This paper presents a new constraint-driven method for computational pattern selection, mapping and application scheduling using reconfigurable processor extensions. The presente...
Kevin Martin, Christophe Wolinski, Krzysztof Kuchc...
HPCA
2006
IEEE
14 years 5 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
PLDI
2000
ACM
13 years 9 months ago
Optimal instruction scheduling using integer programming
{ This paper presents a new approach to local instruction scheduling based on integer programming that produces optimal instruction schedules in a reasonable time, even for very la...
Kent D. Wilken, Jack Liu, Mark Heffernan
ASPLOS
2006
ACM
13 years 9 months ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...