Sciweavers

36 search results - page 1 / 8
» An Architecture Framework for Transparent Instruction Set Cu...
Sort
View
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
13 years 10 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
DAC
1999
ACM
14 years 5 months ago
Customized Instruction-Sets for Embedded Processors
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
Joseph A. Fisher
CASES
2005
ACM
13 years 6 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
MICRO
2003
IEEE
95views Hardware» more  MICRO 2003»
13 years 9 months ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded appl...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
13 years 8 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi