89 search results - page 1 / 18 » An Architecture for Combined Test Data Compression and Abort... |
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
This paper introduces GECOM technology, a novel test compression method with seamless integration of test GE
ET
2002
13 years 4 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...