89 search results - page 2 / 18 » An Architecture for Combined Test Data Compression and Abort... |
ATS
2003
IEEE
13 years 9 months ago
2003
IEEE
: Most of the recently discussed test stimulus data compression techniques are based on the low care bit densities found in typical scan test vectors. Data reduction primarily is a...
VLSID
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DATE
2008
IEEE
2008
IEEE
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
13 years 6 months ago
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
: Most of the recently discussed and commercially introduced test stimulus data compression techniques are based on low care bit densities found in typical scan test vectors. Data ...