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    FMCAD
    2009
    Springer
    105views Formal Methods» more  FMCAD 2009»
    Scaling VLSI design debugging with interpolation
    14 years 10 days ago
    Scaling VLSI design debugging with interpolation
    Download  www.eecg.toronto.edu
    —Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
    Brian Keng, Andreas G. Veneris
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    DAC
    2001
    ACM
    163views Computer Architecture» more  DAC 2001»
    Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
    14 years 6 months ago
    Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
    Download  reference.kfupm.edu.sa
    roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
    Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukul...
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