A fast asynchronous shift register is used as the serializer and de-serializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR e...
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Ko...
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
Asynchronous quasi-delay-insensitive (QDI) NoCs have several advantages over their clocked counterparts. Virtual channel (VC) is the most utilized flow control method in asynchro...
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
Elisabeth Berrebi, Polen Kission, Serge Vernalde, ...
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...