39 search results - page 1 / 8 » An Automatic Test Pattern Generator for Large Sequential Cir... |
ITC
1994
IEEE
13 years 8 months ago
1994
IEEE
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
VLSID
1997
IEEE
13 years 9 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...