10 search results - page 1 / 2 » An Effective Cache Overlapping Storage Structure for SMT Pro... |
ACISICIS
2005
IEEE
13 years 10 months ago
2005
IEEE
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
ARCS
2006
Springer
13 years 8 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...