70 search results - page 1 / 14 » An Effective Power Management Scheme for RTL Design Based on... |
DAC
1996
ACM
13 years 9 months ago
1996
ACM
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...