62 search results - page 1 / 13 » An Efficient Fault-Tolerant VLSI Architecture Using Parallel... |
EH
2004
IEEE
13 years 8 months ago
2004
IEEE
PPSN
2004
Springer
13 years 10 months ago
2004
Springer
We present a new approach that is able to produce an increased fault tolerance in bio-inspired electronic circuits. To this end, we designed hardwarefriendly genetic regulatory net...
MSS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
HPDC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper reports on the architecture and design of Starfish, an environment for executing dynamic (and static) MPI-2 programs on a cluster of workstations. Starfish is unique in ...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...