39 search results - page 3 / 8 » An Efficient Hardware Architecture without Line Memories for... |
CGF
2010
13 years 6 months ago
2010
We present a flexible and highly efficient hardware-assisted volume renderer grounded on the original Projected Tetrahedra (PT) algorithm. Unlike recent similar approaches, our me...
ISPASS
2007
IEEE
14 years 13 days ago
2007
IEEE
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
JRTIP
2008
13 years 6 months ago
2008
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
ICIP
2009
IEEE
14 years 7 months ago
2009
IEEE
In implementing an efficient block coder for JPEG2000, the memories required for storing the state variables dominate the hardware cost of a block coder. In this paper, we propose...