Sciweavers

8 search results - page 1 / 2
» An ILP formulation for task mapping and scheduling on multi-...
Sort
View
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
13 years 11 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
DSD
2008
IEEE
104views Hardware» more  DSD 2008»
13 years 4 months ago
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
Efficient utilization of multi-core architectures relies on the partitioning of applications into tasks and mapping the tasks to cores. In some applications (e.g. H.264 video deco...
Magnus Själander, Andrei Terechko, Marc Duran...
CASES
2006
ACM
13 years 10 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
CGO
2009
IEEE
13 years 11 months ago
Software Pipelined Execution of Stream Programs on GPUs
—The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. This model allows programmers to sp...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
PDP
2011
IEEE
12 years 8 months ago
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
Jia Huang, Christian Buckl, Andreas Raabe, Alois K...