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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
13 years 9 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
HIPC
2000
Springer
13 years 8 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
13 years 8 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
13 years 8 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
DAC
1994
ACM
13 years 8 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain