54 search results - page 1 / 11 » An Instruction Throughput Model of Superscalar Processors |
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
INFOVIS
1999
IEEE
13 years 9 months ago
1999
IEEE
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and c...