126 search results - page 1 / 26 » An Integrated Framework for the Design and Optimization of S... |
ET
2002
13 years 4 months ago
2002
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
DATE
2007
IEEE
13 years 10 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...