25 search results - page 1 / 5 » An O(n) Algorithm for Transistor Stacking with Performance C... |
DAC
1996
ACM
13 years 9 months ago
1996
ACM
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
VLSID
1997
IEEE
13 years 9 months ago
1997
IEEE
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...