13 search results - page 1 / 3 » An algorithm for the verification of timing diagrams realiza... |
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper, we present a new method for verifying the realizability of a timing diagram with linear timing constraints, thus ensuring that the implementation of the underlying ...
FMCAD
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
APN
2006
Springer
13 years 6 months ago
2006
Springer
Program verification is usually done by adding specifications and invariants to the program and then proving that the verification conditions are all true. This makes program verif...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...