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ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 1 months ago
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...
TCAD
2002
98views more  TCAD 2002»
13 years 4 months ago
An Esterel compiler for large control-dominated systems
Embedded hard real-time software systems often need fine-grained parallelism and precise control of timing, things typical real-time operating systems do not provide. The Esterel l...
Stephen A. Edwards
CGO
2004
IEEE
13 years 8 months ago
Optimizing Translation Out of SSA Using Renaming Constraints
Static Single Assignment form is an intermediate representation that uses instructions to merge values at each confluent point of the control flow graph. instructions are not ma...
Fabrice Rastello, François de Ferriè...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 4 months ago
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chos...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
RTSS
1992
IEEE
13 years 8 months ago
Allocation of periodic task modules with precedence and deadline constraints in distributed real-time systems
This paper addresses the problem of allocating (assigning and scheduling) periodic task modules to processing nodes in distributed real-time systems subject to task precedence and ...
Chao-Ju Hou, Kang G. Shin