149 search results - page 1 / 30 » An approach for implementing efficient superscalar CISC proc... |
HPCA
2006
IEEE
14 years 4 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
SIPEW
2009
Springer
13 years 11 months ago
2009
Springer
The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions i...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...