106 search results - page 1 / 22 » An approach for reducing dynamic power consumption in synchr... |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...