38 search results - page 2 / 8 » An empirical evaluation of high level transformations for em... |
SC
1992
ACM
13 years 9 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
ARCS
2009
Springer
14 years 3 days ago
2009
Springer
Abstract. Java is widely deployed on a variety of processor architectures. Consequently, an understanding of microarchitecture level Java performance is critical to optimize curren...
LCTRTS
2005
Springer
13 years 11 months ago
2005
Springer
Efficient implementation of DSP applications is critical for many embedded systems. Optimising C compilers for embedded processors largely focus on code generation and instructio...
DATE
2008
IEEE
14 years 2 hour ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...