Sciweavers

    1 search results - page 1 / 1
    » An implementation of an asychronous FPGA based on LEDR four-...
    Sort
    View
    ASPDAC
    2011
    ACM
    215views Hardware» more  ASPDAC 2011»
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    12 years 8 months ago
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    Download  www.kameyama.ecei.tohoku.ac.jp
    —This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
    Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.