As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
—In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes...
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...