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ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
14 years 1 months ago
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Saraju P. Mohanty, Elias Kougianos
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
13 years 10 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
13 years 10 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...