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ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 7 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
DAC
2002
ACM
14 years 6 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
CODES
2007
IEEE
13 years 12 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
EMSOFT
2007
Springer
13 years 9 months ago
Verification of device drivers and intelligent controllers: a case study
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...
David Monniaux
SIGMETRICS
2004
ACM
124views Hardware» more  SIGMETRICS 2004»
13 years 11 months ago
Interposed proportional sharing for a storage service utility
This paper develops and evaluates new share-based scheduling algorithms for differentiated service quality in network services, such as network storage servers. This form of resou...
Wei Jin, Jeffrey S. Chase, Jasleen Kaur