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» Analysis of Performance Impact Caused by Power Supply Noise ...
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DAC
1997
ACM
13 years 8 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
VTS
2000
IEEE
167views Hardware» more  VTS 2000»
13 years 8 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
VTS
2002
IEEE
128views Hardware» more  VTS 2002»
13 years 9 months ago
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
13 years 10 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram