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» Analysis of a reconfigurable network processor
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ERSA
2009
146views Hardware» more  ERSA 2009»
13 years 3 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
AINA
2006
IEEE
13 years 10 months ago
Supporting Runtime Reconfiguration on Network Processors
Network Processors (NPs) are set to play a key role in the next generation of networking technology. They have the performance of ASIC-based routers whilst offering a high degree o...
Kevin Lee, Geoffrey Coulson
JCP
2007
154views more  JCP 2007»
13 years 6 months ago
Partially Reconfigurable Vector Processor for Embedded Applications
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
Muhammad Z. Hasan, Sotirios G. Ziavras
FCCM
2006
IEEE
201views VLSI» more  FCCM 2006»
13 years 9 months ago
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...
Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor...
FCCM
1998
IEEE
79views VLSI» more  FCCM 1998»
13 years 10 months ago
RENCO: A Reconfigurable Network Computer
Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo ...