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» Analysis of buffered hybrid structured clock networks
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ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
14 years 1 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 1 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
13 years 10 months ago
Statistical Analysis of Clock Skew Variation in H-Tree Structure
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi O...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
13 years 10 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman